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		<div class="tab">Verilog 教程</div>
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				<h2>6.6 Verilog 仿真激励</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog" title="Verilog 教程" >Verilog 教程</a> </h3>
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					<h3>关键词：testbench，仿真，文件读写</h3>
<p>Verilog 代码设计完成后，还需要进行重要的步骤，即逻辑功能仿真。仿真激励文件称之为 testbench，放在各设计模块的顶层，以便对模块进行系统性的例化调用进行仿真。</p>
<p>毫不夸张的说，对于稍微复杂的 Verilog 设计，如果不进行仿真，即便是经验丰富的老手，99.9999% 以上的设计都不会正常的工作。不能说仿真比设计更加的重要，但是一般来说，仿真花费的时间会比设计花费的时间要多。有时候，考虑到各种应用场景，testbench 的编写也会比 Verilog 设计更加的复杂。所以，数字电路行业会具体划分设计工程师和验证工程师。</p>
<p>下面，对 testbench 做一个简单的学习。</p>
<h3>
testbench 结构划分</h3>
testbench 一般结构如下:
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2020/09/VuJtsmlLrJjDTWDO.png" ></p><p>
其实 testbench 最基本的结构包括信号声明、激励和模块例化。</p><p>
根据设计的复杂度，需要引入时钟和复位部分。当然更为复杂的设计，激励部分也会更加复杂。根据自己的验证需求，选择是否需要自校验和停止仿真部分。</p><p>
当然，复位和时钟产生部分，也可以看做激励，所以它们都可以在一个语句块中实现。也可以拿自校验的结果，作为结束仿真的条件。</p><p>
实际仿真时，可以根据自己的个人习惯来编写 testbench，这里只是做一份个人的总结。</p>
<h3>
testbench 仿真举例</h3><p>
前面的章节中，已经写过很多的 testbench。其实它们的结构也都大致相同。</p><p>下面，我们举一个数据拼接的简单例子，对 testbench 再做一个具体的分析。</p>
<p>一个 2bit 数据拼接成 8bit 数据的功能模块描述如下:</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> &nbsp;data_consolidation<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rstn <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; din <span style="color: #5D478B;">,</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//data in</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; din_en <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;dout <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;dout_en &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//data out</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">// data shift and counter</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;data_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;state_cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; state_cnt &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; data_r &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>din_en<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; state_cnt &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> state_cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//数据计数</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; data_r &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">&lt;=</span> <span style="color: #9F79EE;">&#123;</span>data_r<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">5</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> din<span style="color: #9F79EE;">&#125;</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//数据拼接</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; state_cnt <span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">assign</span> dout &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> data_r <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">// data output en</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;dout_en_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk <span style="color: #A52A2A; font-weight: bold;">or</span> <span style="color: #A52A2A; font-weight: bold;">negedge</span> rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; dout_en_r &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//计数为 3 且第 4 个数据输入时，同步输出数据输出使能信号</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>state_cnt <span style="color: #5D478B;">==</span> <span style="color: #ff0055;">2'd3</span> <span style="color: #5D478B;">&amp;</span> din_en<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> &nbsp;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; dout_en_r &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; dout_en_r &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//这里不直接声明dout_en为reg变量，而是用相关寄存器对其进行assign赋值</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">assign</span> dout_en &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> dout_en_r<span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>对应的 testbench 描述如下，增加了文件读写的语句:</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #008800;">`timescale</span> <span style="color: #ff0055;">1ns</span><span style="color: #5D478B;">/</span><span style="color: #ff0055;">1ps</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//============== (1) ==================</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//signals declaration</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> test <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk<span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;rstn <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;din <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;din_en <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; dout <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; dout_en <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (2) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//clock generating</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">real</span> &nbsp; &nbsp; &nbsp; &nbsp; CYCLE_200MHz <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">5</span> <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_200MHz<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_200MHz<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (3) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//reset generating</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; rstn &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">8</span> rstn &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (4) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//motivation</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">int</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;fd_rd <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;data_in_temp <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//for self check</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">15</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; read_temp <span style="color: #5D478B;">;</span> &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//8bit ascii data, 8bit \n</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; din_en &nbsp; &nbsp;<span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//(4.1)</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; din &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; open_file<span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;../tb/data_in.dat&quot;</span><span style="color: #5D478B;">,</span> <span style="color: #FF00FF;">&quot;r&quot;</span><span style="color: #5D478B;">,</span> fd_rd<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//(4.2)</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wait</span> <span style="color: #9F79EE;">&#40;</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//(4.3)</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span> CYCLE_200MHz <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//read data from file</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">while</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span> <span style="color: #9932CC;">$feof</span><span style="color: #9F79EE;">&#40;</span>fd_rd<span style="color: #9F79EE;">&#41;</span> <span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span> &nbsp;<span style="color: #00008B; font-style: italic;">//(4.4)</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$fread</span><span style="color: #9F79EE;">&#40;</span>read_temp<span style="color: #5D478B;">,</span> fd_rd<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; din &nbsp; &nbsp;<span style="color: #5D478B;">=</span> read_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">9</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">8</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; data_in_temp <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#123;</span>data_in_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">5</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> din<span style="color: #9F79EE;">&#125;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; din_en <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//stop data</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//(4.5)</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">2</span> din_en <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//open task</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">task</span> open_file<span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #A52A2A; font-weight: bold;">string</span> &nbsp; &nbsp; &nbsp;file_dir_name <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #A52A2A; font-weight: bold;">string</span> &nbsp; &nbsp; &nbsp;rw <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">int</span> &nbsp; &nbsp; &nbsp; &nbsp;fd <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; &nbsp; &nbsp; fd <span style="color: #5D478B;">=</span> <span style="color: #9932CC;">$fopen</span><span style="color: #9F79EE;">&#40;</span>file_dir_name<span style="color: #5D478B;">,</span> rw<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span> fd<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;--- iii --- Failed to open file: %s&quot;</span><span style="color: #5D478B;">,</span> file_dir_name<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;--- iii --- %s has been opened successfully.&quot;</span><span style="color: #5D478B;">,</span> file_dir_name<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">endtask</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (5) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//module instantiation</span><br />
&nbsp; &nbsp; data_consolidation &nbsp; &nbsp;u_data_process<br />
&nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; .clk &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>clk<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; .rstn &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>rstn<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; .din &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>din<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; .din_en &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>din_en<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; .dout &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>dout<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; .dout_en &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>dout_en<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (6) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//auto check</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; err_cnt <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">int</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;fd_wr <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; err_cnt &nbsp; <span style="color: #5D478B;">=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; open_file<span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;../tb/data_out.dat&quot;</span><span style="color: #5D478B;">,</span> <span style="color: #FF00FF;">&quot;w&quot;</span><span style="color: #5D478B;">,</span> fd_wr<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>dout_en<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$fdisplay</span><span style="color: #9F79EE;">&#40;</span>fd_wr<span style="color: #5D478B;">,</span> <span style="color: #FF00FF;">&quot;%h&quot;</span><span style="color: #5D478B;">,</span> dout<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>dout_en<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>data_in_temp <span style="color: #5D478B;">!=</span> dout<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; err_cnt <span style="color: #5D478B;">=</span> err_cnt <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//============== (7) ==================</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//simulation finish</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">10000</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">!</span>err_cnt<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;-------------------------------------&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;Data process is OK!!!&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;-------------------------------------&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;-------------------------------------&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;Error occurs in data process!!!&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$display</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;-------------------------------------&quot;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$finish</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span> <span style="color: #00008B; font-style: italic;">// test</span><br />
</div></div>
<p>仿真结果如下。由图可知，数据整合功能的设计符合要求:</p><p>
<a href="../wp-content/uploads/2020/09/Yp7UIofA10Bynfgh.png" target="_blank" rel="noopener noreferrer"><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2020/09/Yp7UIofA10Bynfgh.png" /></a></p>
<h3>
testbench 具体分析</h3>
<p><strong>1）信号声明</strong></p><p>
testbench 模块声明时，一般不需要声明端口。因为激励信号一般都在 testbench 模块内部，没有外部信号。</p><p>
声明的变量应该能全部对应被测试模块的端口。当然，变量不一定要与被测试模块端口名字一样。但是被测试模块输入端对应的变量应该声明为 reg 型，如 clk，rstn 等，输出端对应的变量应该声明为 wire 型，如 dout，dout_en。</p>
<p><strong>
2）时钟生成</strong></p>
<p>生成时钟的方式有很多种，例如以下两种生成方式也可以借鉴。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">initial</span> clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_200MHz<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> clk <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>clk<span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_200MHz<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> clk <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>clk<span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">end</span> &nbsp; &nbsp; &nbsp; <br />
</div></div>
<p>需要注意的是，利用取反方法产生时钟时，一定要给 clk 寄存器赋初值。</p><p>
利用参数的方法去指定时间延迟时，如果延时参数为浮点数，该参数不要声明为 parameter 类型。例如实例中变量 CYCLE_200MHz 的值为 2.5。如果其变量类型为 parameter，最后生成的时钟周期很可能就是 4ns。当然，timescale 的精度也需要提高，单位和精度不能一样，否则小数部分的时间延迟赋值也将不起作用。</p>
<p><strong>
3）复位生成</strong></p><p>
复位逻辑比较简单，一般赋初值为 0，再经过一段小延迟后，复位为 1 即可。</p><p>
这里大多数的仿真都是用的低有效复位。</p>
<p><strong>
4）激励部分</strong></p><p>
激励部分该产生怎样的输入信号，是根据被测模块的需要来设计的。</p><p>
本次实例中:</p>
<ul><li>
(4.1) 对被测模块的输入信号进行一个初始化，防止不确定值 X 的出现。激励数据的产生，我们需要从数据文件内读入。</li><li>
(4.2) 处利用一个 task 去打开一个文件，只要指定文件存在，就可以得到一个不为 0 的句柄信号 fp_rd。fp_rd 指定了文件数据的起始地址。</li><li>
(4.3) 的操作是为了等待复位后，系统有一个安全稳定的可测试状态。</li><li>
(4.4) 开始循环读数据、给激励。在时钟下降沿送出数据，是为了被测试模块能更好的在上升沿采样数据。</li></ul>
<p>利用系统任务 $fread ，通过句柄信号 fd_rd 将读取的 16bit 数据变量送入到 read_temp 缓存。</p><p>
输入数据文件前几个数据截图如下。因为 $fread 只能读取 2 进制文件，所以输入文件的第一行对应的 ASCII 码应该是 330a，所以我们想要得到文件里的数据 3，应该取变量 read_temp 的第 9 到第 8bit 位的数据。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2020/09/euf9p6G8WbZxlyt0.png"></p>

<p>信号 data_in_temp 是对输入数据信号的一个紧随的整合，后面校验模块会以此为参考，来判断仿真是否正常，模块设计是否正确。</p><ul><li>
(4.5) 选择在时钟上升沿延迟 2 个周期后停止输入数据，是为了被测试模块能够正常的采样到最后一个数据使能信号，并对数据进行正常的整合。</li></ul>
<p>当数据量相对较少时，可以利用 Verilog 中的系统任务 $readmemh 来按行直接读取 16 进制数据。保持文件 data_in.dat 内数据和格式不变，则该激励部分可以描述为：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;data_mem <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">39</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;data_in_temp <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//for self check</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">integer</span> &nbsp; &nbsp; &nbsp;k1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; din_en &nbsp; &nbsp;<span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; din &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> 'b0 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$readmemh</span><span style="color: #9F79EE;">&#40;</span><span style="color: #FF00FF;">&quot;../tb/data_in.dat&quot;</span><span style="color: #5D478B;">,</span> data_mem<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wait</span> <span style="color: #9F79EE;">&#40;</span>rstn<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span> CYCLE_200MHz <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//read data from file</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">for</span><span style="color: #9F79EE;">&#40;</span>k1<span style="color: #5D478B;">=</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">;</span> k1<span style="color: #5D478B;">&lt;</span><span style="color: #ff0055;">40</span><span style="color: #5D478B;">;</span> k1<span style="color: #5D478B;">=</span>k1<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">negedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; din &nbsp; &nbsp;<span style="color: #5D478B;">=</span> data_mem<span style="color: #9F79EE;">&#91;</span>k1<span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; data_in_temp <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#123;</span>data_in_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">5</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #5D478B;">,</span> din<span style="color: #9F79EE;">&#125;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; din_en <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//stop data</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">2</span> din_en <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>
<p><strong>
5）模块例化</strong></p><p>
这里利用 testbench 开始声明的信号变量，对被测试模块进行例化连接。</p>
<p><strong>
6）自校验</strong></p><p>
如果设计比较简单，完全可以通过输入、输出信号的波形来确定设计是否正确，此部分完全可以删除。如果数据很多，有时候拿肉眼观察并不能对设计的正确性进行一个有效判定。此时加入一个自校验模块，会大大增加仿真的效率。</p><p>
实例中，我们会在数据输出使能 dout_en 有效时，对输出数据 dout 与参考数据 read_temp（激励部分产生）做一个对比，并将对比结果置于信号 err_cnt 中。最后就可以通过观察 err_cnt 信号是否为 0 来直观的对设计的正确性进行判断。</p><p>
当然如实例中所示，我们也可以将数据写入到对应文件中，利用其他方式做对比。</p>
<p><strong>
7）结束仿真</strong></p><p>
如果我们不加入结束仿真部分，仿真就会无限制的运行下去，波形太长有时候并不方便分析。Verilog 中提供了系统任务 $finish 来停止仿真。</p><p>
停止仿真之前，可以将自校验的结果，通过系统任务 $display 在终端进行显示。</p>
<h3>
文件读写选项</h3><p>
用于打开文件的系统任务 $fopen 格式如下：</p><pre>
fd = $fopen("&lt;name_of_file&gt;", "mode")</pre>
<p>
和 C 语言类似，打开方式的选项 "mode" 意义如下：</p>
<table class="reference">
<thead>
<tr><th style="text-align:left;">r</th><th style="text-align:left;">只读打开一个文本文件，只允许读数据。</th></tr></thead>
<tbody><tr><td style="text-align:left;">w</td><td style="text-align:left;">只写打开一个文本文件，只允许写数据。如果文件存在，则原文件内容会被删除。如果文件不存在，则创建新文件。</td></tr><tr><td style="text-align:left;">a</td><td style="text-align:left;">追加打开一个文本文件，并在文件末尾写数据。如果文件如果文件不存在，则创建新文件。</td></tr><tr><td style="text-align:left;">rb</td><td style="text-align:left;">只读打开一个二进制文件，只允许读数据。</td></tr><tr><td style="text-align:left;">wb</td><td style="text-align:left;">只写打开或建立一个二进制文件，只允许写数据。</td></tr><tr><td style="text-align:left;">ab</td><td style="text-align:left;">追加打开一个二进制文件，并在文件末尾写数据。</td></tr><tr><td style="text-align:left;">r+</td><td style="text-align:left;">读写打开一个文本文件，允许读和写</td></tr><tr><td style="text-align:left;">w+</td><td style="text-align:left;">读写打开或建立一个文本文件，允许读写。如果文件存在，则原文件内容会被删除。如果文件不存在，则创建新文件。</td></tr><tr><td style="text-align:left;">a+</td><td style="text-align:left;">读写打开一个文本文件，允许读和写。如果文件不存在，则创建新文件。读取文件会从文件起始地址的开始，写入只能是追加模式。</td></tr><tr><td style="text-align:left;">rb+</td><td style="text-align:left;">读写打开一个二进制文本文件，功能与 "r+" 类似。</td></tr><tr><td style="text-align:left;">wb+</td><td style="text-align:left;">读写打开或建立一个二进制文本文件，功能与 "w+" 类似。</td></tr><tr><td style="text-align:left;">ab+</td><td style="text-align:left;">读写打开一个二进制文本文件，功能与 "a+" 类似。</td></tr></tbody>
</table><h3>源码下载</h3>
<p><a href="../wp-content/uploads/2020/09/6.6sim-file.zip" download class="download">Download</a></p>				</div>
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	<li><a target="_top" data-id="23008" title="6.5 Verilog 避免 Latch" href="../w3cnote/verilog-latch.html" >6.5 Verilog 避免 Latch</a></li>
	
		<li>
	6.6 Verilog 仿真激励	</li>
	
		
	<li><a target="_top" data-id="23015" title="6.7 Verilog 流水线" href="../w3cnote/verilog-pipeline-design.html" >6.7 Verilog 流水线</a></li>
	
		
	<li><a target="_top" data-id="23021" title="7.1 Verilog 除法器设计" href="../w3cnote/verilog-dividend.html" >7.1 Verilog 除法器设计</a></li>
	
		
	<li><a target="_top" data-id="23222" title="7.2 Verilog 并行 FIR 滤波器设计" href="../w3cnote/verilog-fir.html" >7.2 Verilog 并行 FIR 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23230" title="7.3 Verilog 串行 FIR 滤波器设计" href="../w3cnote/verilog-serial-fir.html" >7.3 Verilog 串行 FIR 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23236" title="7.4 Verilog CIC 滤波器设计" href="../w3cnote/verilog-cic.html" >7.4 Verilog CIC 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23260" title="7.5 Verilog FFT 设计" href="../w3cnote/verilog-fft.html" >7.5 Verilog FFT 设计</a></li>
	
		
	<li><a target="_top" data-id="23309" title="7.6 Verilog DDS 设计" href="../w3cnote/verilog-dds.html" >7.6 Verilog DDS 设计</a></li>
	
		
	<li><a target="_top" data-id="23281" title="8.1 Verilog 数值转换" href="../w3cnote/verilog-numerical-conversion.html" >8.1 Verilog 数值转换</a></li>
	
	<li><a target="_top" title="Verilog 教程高级篇" href="../w3cnote/verilog2-tutorial.html" >Verilog 教程高级篇</a></li></ul></div>	</div>
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